The present invention relates to an internal clock generator, a system incorporating the internal clock generator, and a related method of generating an internal clock.
Semiconductor memory devices may be generally classified into volatile memory devices, such as dynamic random access memory (DRAM) and static random access memory (SRAM), and non-volatile memory devices, such as programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), and ferroelectric RAM (FRAM).
A volatile memory device loses stored data when power is interrupted, while a non-volatile memory device retains stored data in the absence of applied power. Non-volatile memory, and in particular contemporary flash memory, is widely used as a recording medium in a variety of devices such as computers and consumer electronics which experience a high probability of interrupted power. Flash memory has a number of additional advantages including relatively high programming speed and low power consumption. As a result, flash memory is commonly used to store the code and/or data implementing certain critical software routines and functionality, such as the so-called basic input/output system (BIOS) or boot code.
Thus, it is common for a flash memory device being used for such purposes to include a boot block storing BIOS code, boot code, and/or related password or access routines. The boot block is a flash memory area (e.g., a defined range of data addresses) that host device processor may access upon system initialization. That is, every time a power voltage Vcc is applied to the host device, the processor will access the BIOS code, or boot code, etc., stored in the boot block. Thus, data in the boot block is accessed (i.e., read, erased, updated, and/or programmed) more frequently that other general data blocks in flash memory.
FIG. 1 illustrates a generic conventional system 100. System 100 includes a controller 120 and a memory 140. Memory 140 includes main data stored in a one or more main data blocks. The software routines implemented by the main data may be executed when power voltage VCC is supplied to the host device. However, such software routines can only be run in usual circumstances after the host device has accessed the boot code, operating system (OS) software, and/or BIOS software (hereafter, collectively or singularly referred to as “boot code”). Thus, once power voltage VCC is supplied to system 100, controller 120 accesses the main data stored in memory 140 only after a predetermined initialization period during which boot code is accessed and corresponding host device initialization procedures are executed.
FIG. 2 illustrates an exemplary approach to the preparation of boot code prior to its being accessed. This “loading” of the boot code begins once power voltage VCC is supplied to system 100. In the illustrated example, system 100 performs boot code loading in response to a power-on reset signal POR actuated following a predetermined wait time TWT. The wait time Twt is a period of time necessary to stabilize and verify certain operating voltages (e.g., VDD) within system 100. That is, the power-on reset signal is actuated once the voltage level of certain voltages necessary to the proper operating of internal circuitry in system 100 has been assured.
In the context of the example illustrated in FIG. 2, once Vdd rises from 0V to at least 1.4V, the power-on reset signal (VPOR) is actuated (i.e., transitions from a logically low state to the logically high state, or goes “high”), controller 120 begins generation of an internal clock signal CLK. With the generation of the internal clock CLK, controller 120 may count out the wait time TWT. After the wait time TWT has expired, controller 120 actuates a boot load signal BLF during a defined boot load time period TBT. Once the boot load signal BLF goes high, controller 120 loads the boot code from memory 140 during the boot load time period TBT.
In some cases, it may take a long time to raise the operating voltage VDD of the system 100 up to a target voltage, e.g., 1.8 V.
FIG. 3 illustrates another example of boot code loading in the conventional system 100. However, unlike the example illustrated in FIG. 2, this example is characterized by a slowly rising operating voltage VDD. In this case, controller 120 must wait considerably longer for the operating voltage VDD to rise to the defined minimum threshold of VPOR=1.4 before initiating the wait time TWT. Again, only after expiration of the wait time TWT can system 100 load the boot code during the boot load time TBT. However, as shown in FIG. 3, the boot code is loaded before the operating voltage VDD reaches its desired level of 1.8 V. In such a circumstance, the internal circuitry of system 100 may not operate properly
Thus, if the operating voltage remains low after the wait time during which the internal clock CLK has been spun up, certain logic circuitry such as data latches, for example, may not operate properly despite the presence of a properly configured internal clock CLK. That is, the spin up of the internal clock CLK and one or more of the operating voltages is poorly synchronized and overall system performance suffers. Indeed, where memory or data latch components used to load the boot code fail under the effects of low operating voltage(s), the boot code loading operating may completely fail.